Emulation Technical Leader
Core
Architecting pre-silicon emulation roadmap and defining DFT emulation strategy for Silicon One's complex ASICs.
Role type
Senior IC DFT Emulation Technical Leader
Builds
Pre-silicon emulation infrastructure for multi-terabit networking ASICs
Domain
Semiconductor hardware design / ASIC validation
Deliverable
production ML models | product features | infrastructure
Required skills
DFT emulation strategy definition, Palladium/Veloce/Zebu platform expertise, Verilog/System Verilog, C/C++, Tcl/Python/Perl scripting
Preferred skills
JTAG protocol, scan architecture, MBIST, boundary scan, UVM, post-silicon validation
Technologies
Palladium, Veloce, Zebu, Verilog, System Verilog, C, C++, Tcl, Python, Perl, UVM
Responsibilities
Define DFT emulation strategy from scratch, build high-performing engineering team, validate complex scan/MBIST/JTAG architectures, drive seamless silicon bring-up
Seniority
Senior, hands-on IC with strategy & mentorship
