ASIC Analog Senior Layout Engineer
Core
Architecting physical blueprints for next-gen 100G–400G optical interconnects and owning block-to-top integration for AI and data center infrastructure.
Role type
Senior IC ASIC Analog Layout Engineer
Builds
Custom analog and mixed-signal layouts for 100G–400G/lambda optical solutions
Domain
Semiconductor / Optical Interconnects / AI Infrastructure
Required skills
Custom analog layout design, Physical verification, FINFET process expertise (7nm/5nm/3nm), Cadence Virtuoso, Block-level integration, Tapeout execution
Preferred skills
Device-level layout techniques (matching, symmetry, shielding), Parasitic control, Thermal management, Signal integrity, TSMC 2nm experience, EDA signoff flows (DRC/LVS/ERC/EM/IR), Layout automation scripting (Python/Perl/TCL)
Technologies
Cadence Virtuoso, Calibre, Linux, Python, Perl, TCL
Responsibilities
Build and optimize complex analog and mixed-signal layouts for 100G–400G optical solutions, Drive full-flow execution from floorplanning through tapeout and silicon bring-up, Solve high-speed challenges involving parasitics and signal integrity, Shape design methodologies and mentor engineering talent
Seniority
Senior, hands-on IC
