Junior DFT Engineer- ETR- Israel
Core
Design test structures embedded within chips to detect manufacturing defects and filter faulty units before market release.
Role type
Junior DFT Engineer
Builds
Chips with embedded test structures
Domain
Semiconductor design / Hardware verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT logic insertion, synthesis, Automatic Test Pattern Generation (ATPG), Gate Level Simulation, timing checks, DRC checks, regression testing, debugging
Preferred skills
Ability to ramp quickly on interdisciplinary domains
Technologies
Synthesis tools, ATPG tools, Gate Level Simulation environments
Responsibilities
Insert DFT logic, perform synthesis, run ATPG, execute Gate Level Simulations, perform timing and DRC checks, run regressions, debug simulation failures
Seniority
Junior, mentored IC
