Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years
Core
Lead ASIC design verification teams to deliver high-performance, high-quality ASICs and SoCs for Cisco's Enterprise and Service Provider platforms.
Role type
Senior IC ASIC Design Verification Leader (Manager)
Builds
Complex ASICs and SoCs for networking hardware
Domain
Semiconductor / Networking / Hardware
Deliverable
production ML models | product features
Required skills
ASIC/SoC development cycle, System Verilog, UVM methodology, C++, hardware emulation, test plan generation, functional coverage analysis, team leadership, cross-functional collaboration
Preferred skills
DV architecture strategy definition, flow automation (scripting/Makefiles), mentoring senior resources, system-level integration, hardware bring-up
Technologies
System Verilog, UVM, C++, C, EVE, Veloce
Responsibilities
Lead ASIC engineering teams to deliver high-performance ASICs; Define and verify ASIC subsystems; Drive cross-functional collaboration for high-volume production; Collaborate with design and hardware teams on simulation, emulation, and bring-up; Build and enhance UVM/System Verilog testbenches; Define new DV methodologies; Generate and execute test plans; Lead team mentoring and technical decision-making
Seniority
Senior, hands-on IC with management responsibilities
