Leader, ASIC Engineering | RTL, Datapath, Network Processing Unit
Core
Lead ASIC engineering teams to design, verify, and deliver high-performance, power-efficient ASICs and subsystems for Cisco's Enterprise and Service Provider platforms.
Role type
Senior IC ASIC Engineering Leader (RTL, Datapath, Network Processing Unit)
Builds
High-volume production ASICs and complex network processing units
Domain
Networking hardware / ASIC design
Deliverable
production ML models | product features
Required skills
RTL design (Verilog, System Verilog), ASIC/SoC development lifecycle, timing analysis, power optimization, formal verification, CDC, gate-level synthesis, system debug, SW/HW bring-up
Preferred skills
Architecture review leadership, complex system-level integration, mentoring senior resources, design execution strategy
Technologies
VCS, Spyglass
Responsibilities
Lead teams to define and design ASICs meeting PPA goals; drive cross-functional collaboration for high-volume production; define design processes and tools; oversee documentation and validation; conduct design reviews and technical decision-making; mentor team on architectural strategies
Seniority
Senior, hands-on IC with leadership
