ASIC Verification Technical Leader
Core
Lead ASIC verification for Cisco's Silicon One architecture, focusing on block, cluster, and top-level environments for core switching, routing, and wireless products.
Role type
Senior IC ASIC Verification Technical Leader
Builds
Sophisticated ASICs for data center, enterprise, and service provider networking hardware
Domain
Networking hardware / ASIC design verification
Deliverable
production ML models | product features
Required skills
UVM, System Verilog, constraint random verification, Perl/Python scripting, RTL qualification, Gate Level Simulation, emulation support, post-silicon bring-up debugging
Preferred skills
Networking ASICs, Forwarding logic/Parsers/Buffer management/Arbitration, Veloce/Palladium/Zebu/HAPS, Formal verification, PCIe/Ethernet/RDMA/IPv4/6/TCP protocols
Technologies
UVM, System Verilog, Perl, Python, Zebu, HAPS, Veloce, Palladium
Responsibilities
Architect block, cluster and top-level DV environment infrastructure; Develop DV infrastructure from scratch; Maintain and improve existing DV environments; Develop test plans and tests with constraint random and advised stimulus; Ensure complete verification coverage; Qualify design with Gate Level Simulations; Collaborate with designers and software teams for post-silicon bring-up; Support testing in emulation; Lead ASIC bring-up process
Seniority
Senior, hands-on IC
