ASIC Verification Technical Leader
Core
Architect and develop verification infrastructure for sophisticated networking ASICs, ensuring complete coverage and quality from block level to top-level systems.
Role type
Senior IC ASIC Verification Technical Leader
Builds
ASIC verification environments, test plans, and bring-up processes for Cisco Silicon One architecture
Domain
Networking hardware / Silicon design
Required skills
UVM, System Verilog, constraint random verification, Perl scripting, Python scripting, Gate Level Simulation, emulation testing, post-silicon bring-up debugging
Preferred skills
Networking ASICs, Forwarding logic, Veloce/Palladium/Zebu/HAPS, Formal verification, PCIe/Ethernet/RDMA protocols
Technologies
UVM, System Verilog, Perl, Python, Zebu, HAPS, Veloce, Palladium
Responsibilities
Architect block, cluster and top-level DV environment infrastructure; Develop DV infrastructure from scratch; Maintain and improve existing DV environments; Develop test plans and tests for qualifying design; Ensure complete verification coverage; Ensure RTL quality with Gate Level Simulations; Collaborate with designers and software teams for post-silicon bring-up; Support testing in emulation; Lead ASIC bring-up process
Seniority
Senior, hands-on IC
