DFT ASIC Engineering Technical Leader | ATPG | 10 to 14 years | Bangalore
Core
Lead and mentor a team of DFT engineers to design and implement innovative DFT features ensuring high-quality, testable, and manufacturable silicon designs for next-generation network devices.
Role type
Senior DFT ASIC Engineering Technical Leader
Builds
Programmable silicon architecture for high-speed networking, power efficiency, and scalability
Domain
Networking hardware / Silicon design
Required skills
DFT feature design (scan insertion, BIST, boundary scan), team leadership and mentoring, full product lifecycle management, cross-functional collaboration, debugging and root-cause analysis, methodology standardization
Preferred skills
ATPG methodologies, advanced DFT techniques, complex technical project leadership, system-level understanding of networking and silicon solutions
Technologies
ATPG, scan compression, memory BIST
Responsibilities
Lead and develop a team of DFT engineers; Drive the team through the full product lifecycle from pre-silicon design to production qualification; Collaborate with chip architects and verification teams to define DFT strategies; Supervise implementation of ATPG and other advanced DFT techniques; Guide debugging and root-cause analysis of silicon failures; Establish and improve DFT methodologies; Represent the DFT team in cross-functional meetings
Seniority
Senior, hands-on IC with leadership responsibilities
