DFT ASIC Engineering Technical Leader | ATPG | 10 to 14 years | Bangalore
Core
Lead and mentor a team of DFT engineers to design and implement innovative DFT features ensuring high-quality, testable, and manufacturable silicon designs for next-generation network devices.
Role type
Senior IC DFT Technical Leader (ATPG, Scan, BIST)
Builds
Programmable silicon architecture for high-speed networking, 5G, and web-scale markets
Domain
Semiconductor hardware design / Networking infrastructure
Deliverable
production ML models | product features
Required skills
DFT strategy definition, ATPG methodologies, scan insertion, BIST, boundary scan, silicon bring-up, root-cause analysis, team leadership, project planning
Preferred skills
Advanced DFT techniques, standardization of DFT methodologies, cross-functional collaboration, system-level understanding of networking solutions
Technologies
ATPG, Scan Compression, Memory BIST, Boundary Scan
Responsibilities
Lead and mentor DFT engineers; Drive the team through the full product lifecycle; Collaborate with chip architects and verification teams; Supervise implementation of ATPG and scan compression; Guide debugging and root-cause analysis of silicon failures; Establish and improve DFT methodologies
Seniority
Senior, hands-on IC with team leadership
