Senior ASIC Design Engineer
Core
Designing innovative hardware platforms (silicon, optics) for Cisco's core Switching, Routing, and Wireless products to power the AI era.
Role type
Senior ASIC Design Engineer
Builds
Silicon platforms (e.g., Silicon One) for global networking infrastructure
Domain
Semiconductor / Networking Hardware
Deliverable
production ML models | product features
Required skills
Verilog/System Verilog, ASIC design flow, timing closure, power optimization, clock gating, functional coverage analysis, post-silicon validation
Preferred skills
Full ASIC tapeout experience (advanced nodes), strong RTL skills, debug and scripting skills
Technologies
Verilog, System Verilog
Responsibilities
Author design specifications and participate in micro-architecture reviews; Implement Verilog RTL to meet timing, performance, and power requirements; Develop and analyze functional coverage; Collaborate with verification teams to address design corner cases; Work with physical design teams to close timing and place-and-route issues; Perform diagnostic and post silicon validation tests in the lab
Seniority
Senior, hands-on IC
