ASIC Engineering Design Technical Leader
Core
Leading front-end ASIC design and verification for large-scale programmable silicon architectures powering Cisco's routing portfolio.
Role type
Senior IC ASIC Engineering Design Technical Leader
Builds
Unified programmable silicon devices for Cisco's future routing portfolio
Domain
Semiconductor / ASIC Design / Functional Verification
Deliverable
production ML models | product features | infrastructure
Required skills
Micro-architecture specification review, UVM-based verification environment implementation, bug resolution and coverage closure, post-silicon validation, root-cause analysis, team supervision
Preferred skills
MATLAB simulations, bit-exact modeling, mixed-signal systems, GLS knowledge
Technologies
UVM, MATLAB, GLS
Responsibilities
Review micro-architecture specifications, supervise verification team members, implement Verification environment UVM based, collaborate with Design engineers to resolve bugs, work with firmware/Lab teams to verify chip flows, perform debug and post-silicon validation
Seniority
Senior, hands-on IC with mentorship
