ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years
Core
Lead design verification for high-performance ASICs and SoCs, defining methodologies, building testbenches, and ensuring quality from specification through tape-out.
Role type
Senior IC ASIC Design Verification Technical Leader
Builds
Complex ASIC/SoC chips for enterprise and service provider networking solutions
Domain
Semiconductor hardware design verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM methodology, C++, C, hardware emulation platforms, RTL verification, emulation, post-silicon validation, code coverage analysis, team leadership, technical decision making
Preferred skills
DV architecture strategy definition, flow automation scripting, mentoring senior resources, system-level integration, test plan review leadership
Technologies
System Verilog, UVM, C++, C, EVE, Veloce
Responsibilities
Define and build UVM/System Verilog testbenches from scratch or enhance existing ones; Lead and mentor a team of junior engineers; Drive design verification solutions and technical decisions at the program level; Conduct code reviews and postmortems; Execute end-to-end verification of design blocks and full chip integration; Generate and execute test plans; Participate in all phases of ASIC development including RTL verification, emulation, and post-silicon validation
Seniority
Senior, hands-on IC with leadership responsibilities
