ASIC/SoC Physical Design Engineer - 7 to 10 years - Pune
Core
Design and implementation of ASIC/SoC physical designs for high-speed optical transceivers and silicon photonic platforms in advanced CMOS technology nodes.
Role type
Senior IC ASIC/SoC Physical Design Engineer
Builds
High-speed optical transceivers, silicon photonic platforms, and pluggable/Co-packaged Optics (CPO) for data center networking.
Domain
Semiconductor / Silicon Photonics / Data Center Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC/SoC physical design flow, block-level and full-chip implementation, static timing analysis (STA), timing ECOs, power grid design, IR/EM analysis, physical verification, scripting (Python, Perl, TCL, Shell)
Preferred skills
High-speed/high-density macro-dominant block design, functional equivalence checking, debugging EM/IR/RC/glitch issues, automation for QoR tracking
Technologies
Tempus, Tempus ECO, EDA tools, Python, Perl, TCL, Shell Scripts
Responsibilities
Assist in RTL/netlist-to-GDSII implementation, support digital implementation flows and EDA tool debugging, develop hierarchical floorplans and perform timing/power analysis, run back-end signoff checks, collaborate with cross-functional teams, develop automation scripts
Seniority
Senior, hands-on IC
