Technical Lead, Power Analysis and Optimization
Core
Drive power efficiency from microarchitecture through physical implementation for Cisco's core Switching, Routing, and Wireless products, bridging RTL design and silicon power to meet aggressive PPA targets.
Role type
Senior IC Technical Lead (Power Analysis and Optimization)
Builds
Cisco core Switching, Routing, and Wireless hardware platforms
Domain
Semiconductor hardware design (Silicon, Optics, Networking)
Deliverable
production ML models | product features
Required skills
RTL design and optimization, Power modeling, PrimePower RTL, Microarchitecture evaluation, Physical-aware design methodologies, IR drop and droop profiling, Cross-functional technical leadership
Preferred skills
Application-level workload mapping to microarchitecture, High-speed packet switching architectures, Advanced FinFET process nodes (5nm/3nm), Tcl/Python scripting for automation
Technologies
PrimePower, RTL, Tcl, Python, FinFET
Responsibilities
Evaluate ultra-high-bandwidth packet switching microarchitecture using first-principles approaches; Map application-level network traffic patterns to microarchitectural structures to identify power inefficiencies; Develop comprehensive power vectors simulating production-level network switching workloads; Perform precise power analysis focusing on optimizations, IR drop, and droop profiling; Partner with Physical Design teams to propose RTL enhancements based on clock tree structure and implementation choices; Conduct rigorous post-implementation analysis to verify power targets.
Seniority
Senior, hands-on IC with leadership responsibilities
