ASIC Design Verification Engineer - 7+ yrs
Core
Architecting and developing verification infrastructure for sophisticated ASICs used in Cisco's core switching, routing, and wireless products.
Role type
Senior IC ASIC Design Verification Engineer
Builds
ASIC verification environments, test plans, and test benches for block, cluster, and top-level designs.
Domain
Networking hardware / Silicon design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, constraint random stimulus, gate-level simulation, emulation testing, post-silicon bring-up debugging, RTL quality assurance
Preferred skills
Perl scripting, Python scripting, data path verification, performance testing, Synopsis Ethernet VIP, U controller testing integration, formal verification (iev/vc), protocol knowledge (PCIe, Ethernet, RDMA, TCP)
Technologies
UVM, System Verilog, Perl, Python, Synopsis Ethernet VIP, Gate Level Simulation
Responsibilities
Architect block, cluster, and top-level DV environment infrastructure; Develop DV infrastructure from scratch; Maintain and improve existing DV environments; Develop test plans and tests with constraint random and advised stimulus; Ensure complete verification coverage through code and functional coverage review; Qualify design with Gate Level Simulations on netlist; Collaborate with designers and software teams for post-silicon bring-up debugging; Support testing of design in emulation; Lead all aspects of and manage the ASIC bring-up process.
Seniority
Senior, hands-on IC
