ASIC Design Engineering Technical Lead (Hybrid)
Core
Define, design, and take end-to-end Front-End ownership of ASIC subsystems for high-performance silicon deployed in Cisco platforms.
Role type
Senior IC ASIC Design Technical Lead
Builds
Complex, high-performance Silicon ASICs for networking products
Domain
Semiconductor / Networking
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design in Verilog/System Verilog, microarchitecture design, timing/power/area optimization, technical leadership, cross-functional collaboration, debug and root-cause analysis, process definition
Technologies
Verilog, System Verilog
Responsibilities
Design and implement high-frequency, high-performance RTL meeting aggressive targets; Lead design specifications and technical reviews; Drive technical execution across architecture, design, verification, and physical implementation teams; Mentor engineers and elevate engineering rigor; Lead debug and root-cause analysis across simulation and post-silicon validation; Influence system architecture and key design decisions
Seniority
Senior, hands-on IC with mentorship responsibilities
