ASIC DFT Engineering Technical Leader | Scan, ATPG, MBIST
Core
Lead Design-for-Test (DFT) strategy and implementation for high-performance ASICs in Cisco's Silicon One architecture, ensuring testability from RTL through post-silicon validation.
Role type
Senior IC ASIC DFT Technical Lead
Builds
Next-generation networking chips (switching, routing, wireless) for enterprises, service providers, and public sector.
Domain
Semiconductor hardware design, ASIC implementation, networking infrastructure.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture (Scan, ATPG, MBIST), JTAG protocols (P1500, P1687), EDA toolsets (TestMax, Tetramax, Tessent), Gate-level simulation (VCS, SDF), Physical design signoff, Timing closure, Tcl/Python/Perl scripting, Post-silicon validation/debug.
Preferred skills
Verilog design for custom DFT logic, DFT CAD development, Functional verification.
Technologies
VCS, Tcl, Python, Perl, TestMax, Tetramax, Tessent, SDF, ATE.
Responsibilities
Define DFT architecture and drive requirements early in the design cycle; oversee reusable code and infrastructure for testing environments; coordinate integration of DFT into physical design and verification flows; lead technical expertise for physical design functions; interface with vendors on timing closure and electrical planning; develop test vehicles and perform validation.
Seniority
Senior, hands-on IC technical lead
