ASIC Design Verification Technical Leader - Acacia (hybrid)
Required skills
Bachelor's or Master’s degree majoring in Computer Science, Computer Engineering, or Electronic or Electrical Engineering, with 12+ years of experience using the latest ASIC verification methodologies, tools, and scripting/programming languages SystemVerilog/UVM Experience with in house Verification Intellectual Property (VIP) development strategy
Preferred skills
Experience with C++ hybrid test benches Consistent track record of innovation that leads to quantifiable improvements Self-motivation and the ability to implement effectively without supervision Experience leading ASIC technical teams Knowledge of DSP algorithms and modulation techniques such as QAM Lab silicon validation experience Knowledge of Formal Verification methodologies and tools such as Jasper or VCFormal
Technologies
SystemVerilog/UVM C++ hybrid test benches Formal Verification methodologies and tools such as Jasper or VCFormal DSP algorithms and modulation techniques such as QAM
Responsibilities
Lead and develop detailed and comprehensive test plans Lead and develop verification test benches Apply innovative verification techniques to complex designs Supervise the timely execution of test plans by the rest of the team Lead and assist with chip-level design tradeoffs by working with design engineers Participate in the review of design verification coding and coverage metrics Provide technical leadership & mentoring Work collaboratively with the team to develop & incorporate the latest test technologies & processes
Seniority
Senior
Domain
ASIC Design Verification
