ASIC Engineer G08 | Physical implementation | Floor planning | Clock and Power distribution | Exp 4-8 Years | 2008252
Core
Physical implementation of next-generation networking chips in advanced process nodes, driving the backend flow from RTL to GDS with focus on performance and die size optimization.
Role type
Senior ASIC Physical Design Engineer
Builds
Complex networking chips for Enterprise and Service Provider solutions
Domain
Semiconductor / Networking Hardware
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Hierarchical floor planning, Place & route, Timing closure, Power integrity analysis, Physical verification, Equivalence checks, Hard IP integration, Large scale design implementation (>100M gates), Sub-16nm to 3nm technology experience
Preferred skills
CTS strategy development, Timing ECO implementation, Automation script development for STA tools, Multi-mode and multi-corner design convergence, Methodology improvement for physical design flow
Technologies
EDA tools (Tweaker, Primetime), STA tools, Sub-16/14/7/5/3nm process nodes
Responsibilities
Drive hierarchical floor planning, place & route, and timing closure; Perform power integrity analysis and physical verification; Integrate hard IP and manage global signal/I/O planning; Develop and automate physical design methodologies; Execute timing ECOs and sign-off for multi-corner designs.
Seniority
Mid-Senior, hands-on IC