CAD Engineer – EMIR Signoff
Core
Ensure verification and analysis work is completed on complex mixed-signal designs prior to tapeout, focusing on power/EMIR analysis and signoff methodologies.
Role type
Senior IC signoff engineer (mixed-signal/SoC)
Builds
High-performance, power-efficient system-on-chip (SoC) processors for Apple devices
Domain
Semiconductor design, mixed-signal circuits, EDA
Required skills
EMIR analysis (static/dynamic), CAD flows, Perl scripting, Python scripting, mixed-signal design verification, EDA tool configuration, IP reuse, package model handling
Preferred skills
Redhawk, Voltus, Totem, AI/ML for EDA automation, LLM-driven techniques, CMOS analog design, anomaly detection
Technologies
Redhawk, Voltus, Totem, Perl, Python
