CPU Design Timing Engineer
Core
Responsible for timing closure of CPU designs, collaborating with implementation and RTL teams to ensure timing constraints are met.
Role type
CPU Design Timing Engineer
Builds
High-performance CPU hardware
Domain
Semiconductor / CPU Design
Required skills
Scripting (TCL, Perl, Python), Static timing analysis, Physical design verification (LEC, DVS), Multi-clock domain handling, Noise and OCV analysis
Preferred skills
High-performance CPU implementation experience, CPU microarchitecture knowledge, Physical design tools (synthesis, place & route), 1 GHz+ design experience
Technologies
Primetime, Tempus, TCL, Perl, Python
Responsibilities
Develop timing flows with CAD teams, script analysis flows for efficiency, drive timing closure with micro-architects and implementation engineers
Seniority
Mid-level, hands-on IC
