EMIR/Power Integrity Methodology Engineer
Core
Verify power grid integrity for System-on-Chip (SOC) hardware by defining simulation targets and analyzing static IR drop, instantaneous voltage drop (IVD), and power grid noise.
Role type
Power Integrity Methodology Engineer
Builds
Power grid simulation flows and analysis results for new SOC chips
Domain
Semiconductor hardware design / Power Integrity
Required skills
Power grid integrity analysis, Static IR drop analysis, Instantaneous voltage drop (IVD) analysis, Power grid noise analysis, Electro-migration analysis, Simulation flow development, Cross-functional collaboration, Spice simulations, Library characterization
Preferred skills
ASIC design methodology, Physical design implementation, Static Timing Analysis (STA), Redhawk/Voltus tool expertise, Technical writing
Technologies
Redhawk, Voltus, CAD flow, Spice
Responsibilities
Develop experimental flows for power integrity analysis tools using CAD flow; Drive initial assessment of static IR drop, IVD, and power grid noise; Determine settings for SOC analysis including electro-migration/IR/IVD; Work with physical design and timing teams to analyze simulation results; Explore new tools and methodologies for power grid integrity.
Seniority
Mid-level, hands-on IC
