Emulation Verification Engineer
Core
Verification of large Wireless SoCs using advanced emulation environments and mixed signal models on the Palladium platform.
Role type
Senior IC emulation verification engineer
Builds
Verified chip designs for Apple hardware products
Domain
Semiconductor / Chip Design / Wireless SoC
Required skills
System Verilog, Verilog, UVM, Test bench creation, Regression management, Triaging, Palladium platform, Mixed signal modeling, Cross-functional collaboration
Preferred skills
Emulation bring-up and debugging, RTL to Emulation tool flow, Standard Emulator experience (Palladium, Veloce, Zebu), FPGA flow (Xilinx, Altera), Synthesize-able SystemVerilog, SystemVerilog assertions, C/C++ DPI, Scripting (Perl/Python/TCL), Low Power methodologies (UPF), UVM Acceleration
Responsibilities
Porting designs onto the Palladium platform, Executing detailed emulation test plans, Developing monitors and checkers on the emulation platform, Collaborating with Design, Architecture, Power, Silicon Validation, Performance, and SW teams
Seniority
Senior, hands-on IC
