Custom Timing and Verification CAD Engineer
Core
Build and own transistor-level timing verification and formal verification flows for Apple's custom silicon.
Role type
Entry-level Custom Timing and Verification CAD Engineer
Builds
Verification flows and automation scripts for NanoTime and ESP tools
Domain
Semiconductor / Custom IC Design
Required skills
Perl, Python, TCL scripting; Transistor-level digital/custom IC design; Static timing analysis
Preferred skills
NanoTime, ESP, PrimeTime, HSPICE; Dynamic logic and memory arrays; SPICE netlists and parasitic extraction (DSPF/SPF); SystemVerilog RTL and equivalence checking; Cross-functional collaboration; CAD methodology documentation; AI/ML-driven CAD workflows
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