SoC Physical Design Engineer, STA/Timing
Core
Physical implementation of SoC design partitions from netlist to tapeout, focusing on timing closure and debug.
Role type
SoC Physical Design Engineer (STA/Timing)
Builds
SoC chips for Apple hardware products
Domain
Semiconductor / SoC Physical Design
Required skills
Static Timing Analysis (STA), noise and crosstalk analysis, OCV effects, timing ECO implementation, scripting (Perl/TCL), circuit modeling (SPICE), worst-case corner selection
Preferred skills
Large high-performance SoC design in sub-micron technologies, timing closure methodologies, ECO techniques, large design STA
Responsibilities
Debug timing constraints and facilitate logic changes, create timing ECOs for tapeout, implement timing infrastructure, analyze timing paths to identify key issues, create and maintain analysis scripts and methodologies
Seniority
Entry-level, hands-on IC
