CPU Cache Microarchitect/RTL Engineer
Core
Designing high-performance, low-power CPU multi-level cache subsystems and RTL for multi-processor systems.
Role type
Senior IC CPU Cache Microarchitect/RTL Engineer
Builds
Apple Silicon microprocessors (iPhone, iPad, Watch, Vision Pro, Mac)
Domain
Semiconductor / CPU Microarchitecture
Required skills
CPU microprocessor architecture, logic design principles (timing/power), Verilog, VHDL, simulation/emulation, waveform debugging
Preferred skills
Coherence protocols, interconnects, high-performance design techniques, memory subsystem queuing, SRAM design, multiple clock/power domains, prefetchers, replacement policies, DFT strategies, C/C++ programming, Perl/Python
Technologies
Verilog, VHDL, C, C++, Perl, Python
Responsibilities
Develop micro-architecture specifications from high-level exploration to detailed design; own RTL development targeting power, performance, area, and timing; support verification via test bench development, formal methods, and simulation; explore high-performance strategies and correlate with verification teams; implement and verify physical design aspects including timing, area, reliability, testability, and power.
Seniority
Senior, hands-on IC
