RTL Design Engineer
Core
Design, verify, and bring up sophisticated digital and mixed-signal circuits for Apple products.
Role type
Senior IC RTL Design Engineer (mixed-signal)
Builds
High-performance mixed-signal and analog IPs integrated into high-speed digital circuits
Domain
Semiconductor / Mixed-signal silicon design
Required skills
RTL coding (Verilog, SystemVerilog), mixed-signal circuit design, analog circuit behavioral modeling, design verification (assertions, checkers), static timing analysis, DFT, low-power design methodologies, scripting (Perl, Python, JSON), synthesis flows, lab bring-up analysis
Preferred skills
Micro-architecture specification, front-end tool expertise (simulators, linters, CDC, RDC, LEQ, UPF), ECO design flows, digital signal processing fundamentals, GenAI tools for RTL design and validation
Technologies
Verilog, SystemVerilog, Perl, Python, JSON, UPF, LEQ, CDC, RDC
Responsibilities
Specify and micro-architect digital blocks in mixed-signal circuits, write RTL code, participate in design verification and debugging, contribute to lab bring-up via test scripts and data analysis
Seniority
Mid-level to Senior, hands-on IC