ASIC Design Engineer – Fabric/Interconnect
Core
Design and integration of coherent and non-coherent interconnect fabrics (NoC, crossbars) and memory hierarchies into SoC subsystems.
Role type
Senior IC ASIC Design Engineer (Fabric/Interconnect)
Builds
On-chip interconnect architectures and memory blocks for Apple SoCs
Domain
Semiconductor / SoC Design
Required skills
RTL development, NoC topology design, crossbar design, arbitration logic, IP integration, timing closure, power optimization, verification collaboration, synthesis tools, linting, CDC analysis
Preferred skills
Cache coherency protocols (MESI, MOESI), directory-based coherence, large-scale low-power design experience, front-end tooling expertise
Technologies
RTL, NoC, crossbars, synthesis tools, lint, CDC tools
Responsibilities
Design and integrate coherent/non-coherent fabrics into subsystems; Own RTL development, templating, and scripting; Integrate shared IP blocks for memories/hard macros; Collaborate with synthesis/STA teams for timing closure; Partner with power/performance and verification teams for quality; Coordinate with multi-disciplinary groups for on-time delivery
Seniority
Mid-Senior, hands-on IC
