SoC DFT DV Engineer
Core
Developing verification plans and test benches to validate DFT implementation in pre-silicon SoC designs.
Role type
Senior IC SoC DFT/DV Engineer
Builds
Pre-silicon verification flows for System-on-Chip (SoC) products
Domain
Semiconductor hardware design (SoC, Processors, GPU)
Required skills
DFT verification methodologies, coverage analysis, assertions, gate-level simulation, random/directed verification, scripting (Perl/Python/TCL), OOP
Preferred skills
Large processor/GPU/SOC design experience, project execution leadership, logic design knowledge
Technologies
Perl, Python, TCL, UVM (implied by DV context), Synopsys/Cadence tools (implied by DFT/DV)
Responsibilities
Review architecture and design specifications; Extract design features and develop verification plans; Work with designers to verify DFT implementation; Implement test benches and generate constrained random tests; Debug failures and close coverage; Manage verification schedules and support multi-functional efforts; Assist in automation scripts and regressions
Seniority
Senior, hands-on IC
