Emulation Verification Engineer
Core
Porting large SoC designs onto emulation platforms and executing detailed test plans to verify functionality.
Role type
Senior IC emulation verification engineer
Builds
Verified large System-on-Chip (SoC) designs on emulation platforms
Domain
Semiconductor hardware design and verification
Required skills
SoC design verification, emulation platform setup, synthesizable monitor/checker development, test plan creation, low power testing, Verilog/SystemVerilog coding, UVM environment development, random stimulus infrastructure, scripting (Perl/Python/TCL), firmware debugging
Preferred skills
RTL-to-emulation tool flow knowledge, familiarity with Standard Emulators (Palladium, Veloce, Zebu) or FPGA flows, UVM acceleration experience
Technologies
Palladium, Veloce, Zebu, Xilinx, Altera, Verilog, SystemVerilog, UVM, C/C++, Perl, Python, TCL
Responsibilities
Collaborate with Architecture, Design, DV, Silicon Validation, Power, and SW teams to bring up large SoCs on emulation platforms; Develop and apply synthesizable monitors/checkers and stimulus on the emulation platform; Prepare and complete test plans and perform reviews with multi-functional teams; Perform low power testing on the emulation platform; Develop code for design and verification to aid emulation activities; Develop random stimulus infrastructure by reusing existing UVM simulation constraints
Seniority
Senior, hands-on IC
