PLL Design Engineer
Core
Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies.
Role type
Senior IC analog-mixed-signal engineer (PLL/FLL design)
Builds
High-quality, innovative hard IPs for Apple SoC/PHY designs
Domain
Semiconductor / Analog-Mixed Signal Design
Required skills
PLL/FLL and frequency synthesis architecture, DCO/VCO design (RO and LC), Fractional-N, SSC, Spur and Jitter cancellation, band gaps, bias circuits, op-amps, LDOs, feedback and compensation, clocking fundamentals, phase noise and jitter analysis, loop dynamics, System Verilog modeling, behavioral simulation
Preferred skills
RTL design and debugging, scripting, industry-standard design tools, leadership
Technologies
System Verilog, behavioral simulation tools
Responsibilities
Design digital and analog approaches for frequency synthesis, develop System Verilog models for architectural exploration, perform behavioral simulations to analyze loop dynamics, debug RTL designs, ensure thoroughness in problem-solving and systemic impact analysis
Seniority
Senior, hands-on IC