PLL IC Design Engineer - TeraWave
Core
Design and develop integrated Phase-Locked Loops (PLLs) and clocking systems in advanced CMOS/SiGe processes for space communication satellites.
Role type
Senior IC Design Engineer (Analog/RF)
Builds
High-performance PLL circuits and clock distribution systems for TeraWave satellite constellation
Domain
Aerospace / Satellite Communications / Analog IC Design
Deliverable
production ML models | product features
Required skills
Fractional-N PLL design, VCO design, clock domain synchronization, clock tree optimization, mixed-mode simulation, analog/RF building blocks, silicon debugging, AMS flows
Preferred skills
All-Digital PLL (ADPLL) design, sub-sampling PLL design, LDO design, operational amplifier design, device physics
Technologies
Spectre, MATLAB, SystemVerilog, AMS, FinFET CMOS nodes (7nm+)
Responsibilities
Own system and circuit design of PLLs and clock distribution circuits; Develop high-performance PLL circuits using Spectre and AMS flows; Collaborate with RF and SOC system architects to define requirements; Oversee layout, floorplanning, and verification for tape-out; Develop test plans and facilitate bring-up; Investigate and implement fundamental analog building blocks; Mentor junior engineers
Seniority
Senior, hands-on IC
