Principal Analog Design Engineer
Core
Lead the design and development of advanced clock generation, distribution, synchronization, and timing circuits for next-generation SoCs and mixed-signal products.
Role type
Principal Analog Design Engineer (PLL and clocking)
Builds
High-performance PLL, clock generation, clock distribution, and synchronization circuits for advanced semiconductor products
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features
Required skills
PLL and clocking architectures, transistor-level design (VCOs, charge pumps, PFDs, loop filters, clock buffers, bandgap references, current references, OPAMPs, LDOs), jitter and phase noise analysis, EMC/ESD compliance, silicon characterization and validation, ATE characterization, advanced CMOS/FinFET technologies, analog layout, EDA tools (Cadence Virtuoso, ADE, Spectre/SPICE)
Preferred skills
High-speed SerDes, Ethernet PHYs, timing-intensive mixed-signal systems
Responsibilities
Architect, design, and verify high-performance PLL and clock circuits; Own end-to-end analog design execution from specification to silicon bring-up; Develop innovative analog circuit solutions to optimize jitter, phase noise, and power; Drive reliability, EMC/ESD compliance, and yield improvement; Lead technical reviews and mentor junior engineers
Seniority
Principal, hands-on IC design with mentorship
