Principal Engineer, Mixed-Signal Design Engineering
Core
Lead architect for clock generation, distribution, and synchronization in advanced mixed-signal ICs for pin electronic testing and receive path development.
Role type
Principal IC architect (mixed-signal, high-speed CMOS)
Builds
High-performance industrial ICs and heterogeneously integrated systems
Domain
Semiconductor / Mixed-Signal IC Design / High-Speed SerDes
Required skills
Mixed-signal CMOS IC design, PLL design and integration, Multi-GHz clock distribution, Multi-chip synchronization, Phase interpolators, Timing error correction circuits, Analog/RF circuits, SerDes, Signal integrity, MOS device modeling, PCB design, RF measurements
Preferred skills
FinFET tapeout experience, Strong problem-solving abilities
Technologies
CMOS, FinFET, PLL, SerDes, CTLE, PGA, A/D converter
Responsibilities
Lead architecture for clock generation and distribution, Design and debug PLLs, Develop multi-chip synchronization solutions, Design circuits for timing error correction, Assist in receive path architecture including CTLE and A/D converter specifications
Seniority
Principal, hands-on IC architect
