RFIC Layout Engineer
Core
Designing transistor-level layouts for RF and analog circuit blocks within wireless System-on-Chip (SoC) products to ensure high performance and energy efficiency.
Role type
Senior IC RF layout engineer
Builds
Wireless silicon products (SoCs) for consumer electronics
Domain
Semiconductor / RFIC / Analog IC
Required skills
Deep sub-micron CMOS layout (16nm and lower), FinFet technology, LNA/mixer/PLL/PA/ADC/DAC layout, DRC/LVS/DFM verification, electromigration analysis, signal coupling management, floorplanning, CADENCE tools
Preferred skills
Device matching techniques, parasitic minimization, RF shielding, high-frequency routing, guard rings/DNW/PN junctions, process effects (LOD/WPE), CALIBRE scripting, PERL/SKILL scripting, top-level integration leadership
Technologies
CADENCE, CALIBRE, FinFet, 16nm CMOS
Responsibilities
Perform detailed transistor-level layout of RF/analog blocks; collaborate on block and top-level floorplanning; review layouts for power/gnd routing, EM, and signal integrity; manage top-level layout integration and verification schedule.
Seniority
Mid-Senior, hands-on IC
