IP Pixel RTL Design Engineer
Core
Architecting next-generation Apple ISP (Image Signal Processing) IP and implementing complex micro-architecture in RTL.
Role type
Senior IC RTL Design Engineer (ASIC)
Builds
High-performance, area- and power-constrained image processing IP blocks for Apple devices
Domain
Consumer electronics / Image Signal Processing / ASIC Design
Required skills
System Verilog, Verilog, ASIC RTL design methodologies, ASIC verification flows (simulation, testbench), frontend tools (Synthesis, STA), C/C++, Python/Perl/Tcl scripting, industry standard interfaces
Preferred skills
Signal processing design, formal verification methodologies
Technologies
System Verilog, Verilog, Python, Perl, Tcl, Synthesis tools, Static Timing Analysis (STA) tools
Responsibilities
Define specifications for ISP micro-architecture, implement RTL designs, collaborate with CAD and PD teams to flow designs to GDS, establish CAD and design methodologies
Seniority
Senior, hands-on IC
