Camera ISP System Architecture Engineer, up to Staff
Core
Architect and develop advanced Image Signal Processing (ISP) hardware pipelines for high-performance, low-power semiconductor products.
Role type
Senior IC ASIC system architect (ISP)
Builds
ISP ASIC hardware modules and microarchitectures for mobile, IoT, and embedded platforms
Domain
Semiconductor / Image Signal Processing / ASIC Design
Deliverable
production ML models
Required skills
ASIC/RTL design, Verilog/System Verilog, C/C++ modeling, microarchitecture design, PPA optimization, AI imaging algorithms, SoC architecture, low-power design
Preferred skills
Computational photography, 3A tuning (AWB/AEC/AF), SystemC/Python, FPGA flows, AI model optimization (PyTorch/TensorFlow), silicon bring-up
Technologies
Verilog, System Verilog, C, C++, SystemC, Python, PyTorch, TensorFlow, FPGA
Responsibilities
Architect ISP ASIC hardware modules; translate image-quality requirements into efficient microarchitectures; partner with algorithm teams to define hardware constraints; develop C/C++ or SystemC models for validation; participate in RTL design reviews; collaborate with verification and physical design teams; support silicon bring-up and debugging.
Seniority
Senior, hands-on IC
