Senior Digital Verification Engineer
Core
Architect and optimize scalable UVM-based verification environments and toolchains for next-generation imagery sensors (Mobile, AR/VR, Automotive).
Role type
Senior IC verification engineer (ASIC/SoC infrastructure).
Builds
Automated verification ecosystems, regression environments, and simulation workflows for Image Signal Processor (ISP) algorithms and security blocks.
Domain
Semiconductor hardware verification (ASIC/SoC) for sensor products.
Required skills
SystemVerilog, UVM, Python, Perl, Bash/TCSH, Linux, CI/CD pipelines, regression management, AI/ML tool integration.
Preferred skills
ISP algorithms, MIPI/AXI/APB/_AHB protocols, ISO 26262, Machine Learning in verification.
Technologies
Cadence Xcelium, vManager, Indago, Python, Perl, Bash, Linux.
