Camera Design Engineer
Core
Design world-class image and video processing blocks (ASIC) for multimedia cameras.
Role type
Senior IC ASIC design engineer (camera/image processing)
Builds
Core-level IP for image/video processing blocks
Domain
Semiconductor / Multimedia / Image Processing
Required skills
Verilog/VHDL RTL design, Design Verification, Bus protocols (AHB, AXI), Image/Video/Graphics/DSP processing, RTL sanity tools (DRC, CDC, Synthesis, Timing, Low Power)
Preferred skills
System Verilog/System C, ASIC implementation of Image Processing Camera IP, Synthesis and physical design team collaboration, Scripting (TCL/Perl/Python/shell)
Technologies
Verilog, VHDL, System Verilog, System C, AHB, AXI, TCL, Perl, Python, Shell
Responsibilities
Micro-architect/design HW specific to Multimedia and Camera Image, Own and deliver core level IP, RTL design, Run synthesis and review results, Perform design rule checks, low power checks, and cross-clock-domain checks, Evaluate performance, area, power, and system cost tradeoffs, Work with verification engineers to develop test plans and BFMs, Implement and debug tests at module and core levels, Create and maintain design documents
Seniority
Senior, hands-on IC
