Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)
Core
Architect, design, layout, measure, and productize ultra-deep sub-micron-based CMOS analog designs for high-speed optical communications products (25Gb/s) integrating into ASICs.
Role type
Senior IC Design Engineer (Analog/Mixed-Signal)
Builds
High-speed optical transceivers for data center, metro, and long-haul telecommunication networks
Domain
Semiconductor / Optical Communications
Deliverable
production ML models | product features
Required skills
High-speed serial link design, Phase Locked Loops (PLL), Operational Amplifiers (Opamps), Equalization techniques, Clock transmission/propagation, High-performance output drivers, Design for manufacturability, Layout validation
Preferred skills
FinFET and GAA technologies, High-frequency layout (floorplaning, routing), Electromigration and IR drop analysis, Laboratory validation (ESD, test setups), Cadence Virtuoso/Spectre, Calibre, EMX, Matlab
Responsibilities
Lead efforts for a large block on a complex chip, mentor team members, participate in peer review of complex IC designs, collaborate with packaging and hardware design teams to ensure signal and power integrity
Seniority
Senior, hands-on IC with mentorship responsibilities
