Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)
Core
Architect, design, layout, measure, and productize ultra-deep sub-micron-based CMOS products for high-speed optical communications transceivers (25Gb/s) serving data center and telecom networks.
Role type
Senior IC Design Engineer (Analog/Mixed-Signal)
Builds
High-speed optical transceiver ASICs for 100G to 1.6T+ fiber optic transmission
Domain
Semiconductor / Optical Communications
Required skills
High-speed serial link design, Phase Locked Loops (PLL), Opamps and Programmable Gain Amplifiers, Equalization techniques, Clock transmission/propagation, High Performance Output Drivers, Design for manufacturability, Layout validation
Preferred skills
FinFET and GAA technologies, High-frequency layout (floorplaning, passives), ESD practices and test setup construction, Mixed-signal simulations (AMS), Matlab
Technologies
Cadence Virtuoso, Spectre/SpectreX, Calibre, EMX, Matlab
Responsibilities
Lead efforts for a large block on a complex chip, mentor team members, participate in peer review of complex IC designs, collaborate with packaging and hardware design teams for signal/power integrity
Seniority
Senior, hands-on IC with mentorship responsibilities