IP Design Verification Engineer
Core
Develop pre-silicon verification environments and test plans to ensure bug-free first silicon for IP designs.
Role type
Senior IC design verification engineer
Builds
Fully functional first silicon IP designs
Domain
Semiconductor / Digital Logic
Required skills
SystemVerilog, UVM, verification environment development, stimulus generation, checker development, coverage analysis, debug, RTL freeze sign-off
Preferred skills
Python, Perl, TCL, PCIe/DRAM protocols, formal verification, C/C++, lab hands-on debug
Technologies
simulators, waveform viewers, build/run automation, coverage collection tools
Responsibilities
Develop detailed test and coverage plans based on micro-architecture; Develop verification methodology suitable for the IP; Develop verification environment including stimulus, checkers, assertions, and trackers
Seniority
Senior, hands-on IC
