ASIC Verification Engineer - Acacia (Hybrid)
Core
Senior technical lead responsible for verifying highly complex ASICs for next-generation 100G-1.6T coherent optical communications products.
Role type
Senior IC ASIC Verification Technical Lead
Builds
High-speed optical interconnect products (DSP ASICs, silicon photonic PICs, coherent modules) for cloud and service providers
Domain
Semiconductor / Optical Communications
Deliverable
production ML models | product features
Required skills
ASIC verification methodologies, C++, SystemVerilog/UVM, SystemC, test plan development, technical leadership, mentoring
Preferred skills
Formal verification (Jasper/VCFormal), DSP algorithms (QAM), in-house IP development, C++ templates, lab silicon validation
Technologies
SystemVerilog, UVM, SystemC, Jasper, VCFormal, C++
Responsibilities
Lead and develop detailed verification test plans, lead and develop verification test benches, apply innovative verification techniques to complex designs, supervise timely execution of test plans, review design verification coding and coverage metrics, provide technical leadership and mentoring
Seniority
Senior, hands-on IC with leadership responsibilities
