Design Verification Engineer II
Core
Own verification of custom IP blocks or subsystems, developing UVM/Formal environments and applying generative AI to drive quality.
Role type
Design Verification Engineer II (IC)
Builds
Custom IP blocks and subsystems for silicon
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features
Required skills
UVM, System Verilog, Formal verification, Random-stimulus generation, Coverage-driven verification, Python scripting, Generative AI application, Debugging, Test plan development
Preferred skills
Experience with fabric interconnects, Coherency, CHI, AXI, AMBA, PCIe, CXL, Virtualization, Security, Interrupts
Technologies
UVM, System Verilog, Python, Formal verification tools
Responsibilities
Develop UVM-based or Formal verification environments; Run and debug simulations to find bugs; Innovate verification methodologies and tools; Coach and mentor team members; Define verification strategies and test plans with partner teams
Seniority
Mid-level IC Engineer
