Design Verification Engineer
Core
Own verification of components used in Fabric Interconnect, developing UVM-based or Formal verification environments to drive quality and find bugs.
Role type
Design Verification Engineer (Fabric Interconnect)
Builds
Verification environments and test plans for Fabric Interconnect components
Domain
Semiconductor hardware verification, Fabric Interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, Formal verification, Random-stimulus generation, Coverage-driven verification, Python scripting, CHI/AMBA protocols, IP verification lifecycle
Preferred skills
Generative AI application, Mentorship, Tool innovation
Technologies
UVM, System Verilog, Python, CHI, AMBA
Responsibilities
Define verification strategies and test plans with partner teams, run and debug simulations, apply coverage-based techniques to meet goals, mentor others in verification expertise
Seniority
Mid-level to Senior, hands-on IC
