Senior Fabric Design Verification Engineer
Core
Lead verification of complex flows at fabric interconnect or block level, developing UVM-based environments and applying generative AI to drive quality.
Role type
Senior IC fabric design verification engineer
Builds
Production silicon IP and subsystems for chip interconnects and coherence
Domain
Semiconductor hardware design, fabric interconnects, and protocol verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, Python scripting, coverage-driven verification, random-stimulus generation, cross-team technical leadership, generative AI application
Preferred skills
Experience with Coherent Hub Interface (CHI) and AMBA protocols, knowledge of PCIe/CXL/virtualization/security, experience with fabric interconnects or protocol bridges
Technologies
UVM, System Verilog, Python, CHI, AMBA, PCIe, CXL
Responsibilities
Define verification strategies and test plans for complex fabric flows, develop and debug UVM-based simulation environments, apply generative AI solutions to verification tasks, coordinate cross-team work to drive verification closure, mentor team members on verification methodologies
Seniority
Senior, hands-on IC with technical leadership
