Design Verification Engineer
Core
Lead verification of components used in Fabric Interconnect, defining strategies and test plans to ensure design quality.
Role type
Senior IC design verification engineer (fabric interconnect)
Builds
Pre-silicon subsystem or IP verification environments for fabric interconnects
Domain
Semiconductor hardware verification, interconnect protocols
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, formal verification, random-stimulus generation, coverage-driven verification, Python scripting, generative AI application, Coherent Hub Interface (CHI), AMBA protocols, fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, protocol bridges
Preferred skills
Experience with IP/block or subsystem level test plans, debugging failures, coverage signoff, creating/maintaining/integrating test benches and checkers
Technologies
UVM, System Verilog, Python, CHI, AMBA
Responsibilities
Own or lead verification of components used in Fabric Interconnect; Develop UVM-based or Formal verification environments and run/debug simulations; Apply random-stimulus and coverage-based techniques to find bugs; Innovate to improve verification efficiency through methodologies or tools; Coach and mentor others in areas of expertise
Seniority
Mid-level, hands-on IC
