Design Verification Engineer - DDR Memory Subsystem
Core
Own verification of features within Memory Controller IP or Subsystem, developing UVM/Formal environments to drive quality and find bugs.
Role type
Design Verification Engineer (DDR Memory Subsystem)
Builds
Memory Controller IP and Subsystem verification environments
Domain
Semiconductor / Memory / Computer Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, Formal verification, Random-stimulus generation, Coverage-driven verification, Python scripting, Coherent Hub Interface (CHI), AMBA protocols, JEDEC specifications, Memory controller design, Fabric interconnects, Coherency, Security, Interrupts, PCIe, CXL, Protocol bridges
Preferred skills
Generative AI application in verification, Mentorship of junior engineers, Tool/methodology innovation
Technologies
UVM, System Verilog, Python, Formal verification tools
Responsibilities
Define verification strategies and test plans with partner teams, Develop and debug UVM/Formal verification environments, Apply coverage-based techniques to meet test goals, Mentor others in verification expertise, Innovate verification methodologies or tools
Seniority
Mid-level to Senior (1+ years with Master's or 2+ years with Bachelor's)
