Senior Design Verification Engineer - Fabric Interconnect
Core
Lead integration-level verification of Fabric Top designs, focusing on coherency (CHI), PCIe/CXL traffic, and configuration access.
Role type
Senior IC design verification engineer (fabric interconnect)
Builds
High-performance fabric interconnects and coherent systems
Domain
Semiconductor / Hardware Verification
Required skills
UVM, System Verilog, Formal verification, Python scripting, Generative AI application, CHI protocol expertise, AMBA protocol expertise, Fabric interconnect verification, Coherency verification, PCIe/CXL verification, IP verification lifecycle management, Technical leadership
Preferred skills
Experience with virtualization, security, interrupts, protocol bridges, bottom-up scheduling, cross-team coordination
Technologies
UVM, System Verilog, Python, CHI, PCIe, CXL, AMBA
Responsibilities
Define verification strategies and test plans for Fabric Top integration; Develop and debug UVM/System Verilog verification environments; Apply formal methods and AI-based approaches to improve verification efficiency; Mentor team members on verification expertise; Drive verification closure and coordinate work across partner IP, SOC, and VIP teams.
Seniority
Senior, hands-on IC with technical leadership
