Senior Formal Verification Engineer
Core
Define and execute formal verification strategies for complex IPs, subsystems, and SoCs, developing plans based on architecture and microarchitecture specifications.
Role type
Senior IC formal verification engineer
Builds
Complex IPs, subsystems, and SoCs
Domain
Semiconductor / Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, SystemVerilog Assertions (SVA), formal verification tools (Cadence JasperGold, Synopsys VC Formal), digital design fundamentals, computer architecture, SoC design, debugging, coverage analysis, proof convergence
Preferred skills
AI-assisted verification workflows, reusable formal verification components, automation flows, methodology evolution
Technologies
Cadence JasperGold, Synopsys VC Formal
Responsibilities
Develop formal verification plans, create SVA and formal properties, debug counterexamples, drive verification closure, develop reusable components and automation flows, mentor junior engineers
Seniority
Senior, hands-on IC
