Principal Silicon Engineer - System Modeling
Core
System modeling of analog circuits and SerDes interface IP, bridging post-silicon validation (ATE) and design teams while contributing to architectural direction.
Role type
Principal Silicon Engineer (System Modeling)
Builds
Analog circuit models, SerDes interface IP, and validation frameworks for high-speed IOs.
Domain
Semiconductor IC design, Analog/Digital mixed-signal, High-speed SerDes
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog circuit architecture, Deep sub-micron node expertise, Layout optimization, Digital/analog control loop analysis, Post-silicon validation of high-speed IOs, DV waveform debugging, Calibration issue resolution, Circuit simulation (Cadence Spectre, HSPICE), Scripting (Python, Perl)
Preferred skills
None stated
Technologies
Cadence Spectre, HSPICE, Python, Perl, IC5
Responsibilities
System modeling of analog circuits and SerDes interface IP, Post-silicon interface between ATE/Validation and design teams, Co-ordination of debug activities, Contribute to architectural direction and analog circuit level architecture
Seniority
Principal, hands-on IC