Principal Signal & Power Engineer (Die to Die and Chiplet Design)
Core
Design and analyze end-to-end Signal and Power Integrity (SIPI) solutions for high-performance compute and AI SoCs, chiplet architectures, and data center platforms.
Role type
Principal Signal & Power Engineer (Die to Die and Chiplet Design)
Builds
Custom IP, System-on-Chip (SoC) designs, and advanced packaging solutions for HPC and AI systems.
Domain
Semiconductor design, High-Performance Computing (HPC), Advanced Packaging, Chiplet Architecture.
Deliverable
production ML models | product features | infrastructure
Required skills
Signal and Power Integrity (SIPI) modeling, DC/AC/transient simulation, IP design, voltage regulator design, advanced packaging technologies, foundry silicon technologies, OSAT technologies, substrate technologies, system-level interface design, timing budget analysis, power supply induced jitter analysis.
Preferred skills
Cross-functional architecture solution driving, system design decision making, industry landscape knowledge of Silicon-IP, Board technology, and Platform design.
Responsibilities
Implement strategies for D2D, HBM, and system-level interface design; model and simulate SIPI effects for data center processors; validate I/O performance from platform to silicon; collaborate with silicon, platform, motherboard, package, and thermal architects; drive engineering system design decisions across product lines.
Seniority
Principal, hands-on IC with strategic cross-functional leadership.
