Principal Silicon Engineer
Core
Design, verify, and optimize PLL cores for custom SerDes interface IP, managing global clock distribution and low-jitter clocking for high-speed spines.
Role type
Principal Silicon Engineer (High-Speed Clocking/PLL)
Builds
Custom SerDes interface IP with high-speed clocking spines
Domain
Semiconductor / High-Speed SerDes / Analog Mixed-Signal
Deliverable
production ML models | product features
Required skills
PLL design, high-speed clocking, deep sub-micron node design, layout optimization, DV waveform debugging, calibration issue resolution, Python scripting, Perl scripting, Matlab/Simulink, Analog Behavioural Modeling (ABM)
Preferred skills
None stated
Technologies
Python, Perl, Matlab, Simulink
Responsibilities
Design and verify PLL cores for custom SerDes interface IP, review timing reports of critical timing cells, perform simulation and post-layout verification, coordinate with layout designers and modeling designers, own global clock distribution for low jitter clocking across SerDes macro
Seniority
Principal, hands-on IC with strategy & mentorship